The present invention relates to technology of controlling access to a memory from a plurality of modules that perform image processing, communication processing, or the like and particularly to a data processing apparatus that controls access to the memory so that buffer memories can be reduced.
In recent years, more advanced and multiple functionalities of CPU (Central Processing Unit)-equipped systems have been progressing. As one of such systems, a system that supports multimedia can be included.
Under the memory architecture of multimedia system LSI (Large Scale Integrated circuit), it has become impossible to store image data equivalent to one frame in an on-chip memory due to reasons such as enlarged screen sizes supported thereby. Accordingly, it has become common to store image data including intermediate data required for image processing in a large capacity memory such as an DRAM (Dynamic Random Access Memory). As a related technology, there is an invention disclosed in Japanese Patent Laid-Open No. 2006-072832.
Japanese Patent Laid-Open No. 2006-072832 aims to provide an image processing system that can increase the processing speed. The image processing system includes a DRAM that temporarily stores image data; a DRAM control unit that performs read/write control of the DRAM; a plurality of image processing units that perform predefined image processes on the image data; an image input unit; an image output unit; and a cache system provided between the DRAM control unit and the image processing units to transfer the image data. The cache system performs, on the DRAM, a read-ahead operation by prefetching the read address and a write-back operation that collectively writes data later. The image data input from and output to the image processing units, the image input unit, and the image output unit is read from and written into the DRAM by DMA via a read cache or write cache.
When an SDRAM (Synchronous DRAM) is used as the memory of the multimedia system LSI, for example, accesses will concentrate on the SDRAM. Therefore, an improvement in memory access efficiency to the SDRAM becomes the key point in SoC (System on Chip) design. An SDRAM is known as a memory device having a poor random access performance, for which the realization of a long burst access is important to improve the access efficiency.
In addition, a multimedia system LSI has modules for image processing or communication processing mounted thereon, with a buffer SRAM (Static Random Access Memory) being installed in each of these IPs for temporarily storing the data written into and read from the SDRAM.
However, provided that a buffer SRAM to each of the IPs requires a large number of SRAMs, the chip area of the LSI becomes larger. In addition, the circuit size becomes larger if each of the IPs is provided with a bus I/F (Interface). Additionally, if a buffer SRAM is provided to each of the IPs, there arises a problem that it becomes difficult to flexibly adjust the buffer capacity. However, Japanese Patent Laid-Open No. 2006-072832 cannot solve the problems described above.